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 DM74AS651 * DM74AS652 Octal Bus Transceiver and Register
October 1986 Revised July 2003
DM74AS651 * DM74AS652 Octal Bus Transceiver and Register
General Description
These devices incorporate an octal transceiver and an octal D-type register configured to enable transmission of data from bus to bus or internal register to bus. The DM74AS651 offers 64-Industrial grade product guaranteeing performance from -40C to +85C. These bus transceivers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these devices with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The registers in the DM74AS651 and DM74AS652 are edge-triggered D-type flip-flops. On the positive transition of the clock (CAB or CBA), the input data is stored. The SAB and SBA control pins are provided to select whether real-time data or stored data is transferred. A LOW input level selects real-time data and a HIGH level selects stored data. The select controls have a "make before break" configuration to eliminate a glitch which would normally occur in a typical multiplexer during the transition between stored and real-time data. The Enable (GAB and GBA) control pins provide four modes of operation; real-time data transfer from bus A-toB, real-time data transfer from bus B-to-A, real-time bus A and/or B data transfer to internal storage, or internal stored data transfer to bus A and/or B.
Features
s Switching specifications at 50 pF s Switching specifications guaranteed over full temperature and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL process s 3-STATE buffer-type outputs drive bus lines directly s Guaranteed performance over industrial temperature range (-40C to +85C) in 64-grade products
Ordering Code:
Order Number DM74AS651WM DM74AS651NT DM74AS652WM DM74AS652NT Package Number M24B N24C M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
(c) 2003 Fairchild Semiconductor Corporation
DS006325
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DM74AS651 * DM74AS652
Connection Diagram
Function Table
INPUTS GAB GBA CAB CBA SAB SBA DATA I/O (Note 1) A1 THRU A8 L L L L H H H X H H H L L H H L H H H or L H or L X X X X L H H X X (Note 2) X X X X L Output X X H or L H or L X X H X Input X H X X Output Input Input Output Output Input B1 THRU B8 Input Isolation Store A and B Data Real Time B Data to A Bus Stored B Data to A Bus Real Time A Data to B Bus Stored A Data to B Bus Stored A Data to B Bus Isolation Store A and B Data Real Time B Data to A Bus Stored B Data to A Bus Real Time A Data to B Bus Stored A Data to B Bus Stored A Data to B Bus Store A, Hold B Store A in both registers OPERATION OR FUNCTION DM74AS651 DM74AS652
X
X
Input
H or L H or L
& Stored B Data to A Bus & Stored B Data to A Bus

H or L
Unspecified Store A, Hold B (Note 1) Output Store A in both registers
L L
X L
H or L

X X (Note 2)
Unspecified (Note 1) Output
Input Input
Hold A, Store B Store B in both registers
Hold A, Store B Store B in both registers
H = HIGH Level L = LOW Level X = Irrelevant = LOW-to-HIGH Transition Note 1: The data output functions may be enabled or disabled by various signals at the GAB and GBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. Note 2: If the select control is LOW, the clocks can occur simultaneously. If the select control is HIGH, the clocks must be staggered in order to load both registers.
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2
DM74AS651 * DM74AS652
Logic Diagrams
DM74AS651 DM74AS652
Schematics of Inputs and Outputs
Equivalent of All Other Inputs Typical of All DM74AS651, DM74AS652 Outputs
3
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DM74AS651 * DM74AS652
Absolute Maximum Ratings(Note 3)
Supply Voltage Input Voltage Control Inputs I/O Ports Operating Free Air Temperature Range Storage Temperature Range Typical JA N Package M Package 41.1C/W 81.5C/W 7V 5.5V 0C to +70C 7V
-65C to +150C
Note 3: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.
Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL fCLK tWCLK tSU tH TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency Width of Enable Pulse Data Setup Time Data Hold Time Operating Free Air Temperature HIGH LOW 0 5 6 6 0 0 70 Parameter Min 4.5 2 0.8 Nom 5 Max 5.5 Units V V V mA mA MHz ns ns ns
-15
48 90
C
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25C. Symbol Parameter Conditions Min Typ VIK VOH Input Clamp Voltage HIGH Level Output Voltage VCC = 4.5V to 5.5V VOL II IIH IIL IO ICC LOW Level Output Voltage Input Current at Max Input Voltage HIGH Level Input Current LOW Level Input Current Output Drive Current Supply Current VCC = 5.5V, VIH = 2.7V VCC = 5.5V, VIL = 0.4V VCC = 5.5V, VO = 2.25V VCC = 5.5V DM74AS651 Outputs HIGH Outputs LOW Outputs Disabled Outputs HIGH DM74AS652 Outputs LOW Outputs Disabled VCC = 4.5V, IOL = Max VCC = 5.5V VI = 7V VI = 5.5V Control Inputs A or B Ports Control Inputs A or B Ports Control Inputs A or B Ports -30 110 120 130 120 130 130 VCC = 4.5V, II = -18 mA VCC = 4.5V IOH = Max IOH = -3 mA IOH = -2 mA 2 2.4 VCC - 2 0.35 0.5 0.1 0.1 20 70 -0.5 -0.75 -112 185 195 195 195 211 211 mA V mA A mA mA 3.2 V Max -1.2 Units V
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4
DM74AS651 * DM74AS652
DM74AS651 Switching Characteristics
Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Output Enable Time to HIGH Level Output Output Enable Time to LOW Level Output Output Disable Time from HIGH Level Output Output Disable Time from LOW Level Output Output Disable Time to HIGH Level Output Output Disable Time to LOW Level Output Output Disable Time from HIGH Level Output Output Disable Time from LOW Level Output
Note 4: These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
Conditions VCC = 4.5V to 5.5V R1 = R2 = 500 CL = 50 pF
From
To
Min 90 2
Max
Units MHz
8.5 9 8 7 11 9 10 16 9 9 11 16 10 11
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CBA or CAB
A or B 2 2
A or B
B or A 1 2 2 2 3 2 2 3 3
SBA or SAB (Note 4)
A or B
Enable GBA
A
Enable GAB
B 2 2
5
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DM74AS651 * DM74AS652
DM74AS652 Switching Characteristics
Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Output Enable Time to HIGH Level Output Output Enable Time to LOW Level Output Output Disable Time from HIGH Level Output Output Disable Time from LOW Level Output Output Disable Time to HIGH Level Output Output Disable Time to LOW Level Output Output Disable Time from HIGH Level Output Output Disable Time from LOW Level Output
Note 5: These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
Conditions VCC = 4.5V to 5.5V R1 = R2 = 500 CL = 50 pF
From
To
Min 90 2
Max
Units MHz
8.5 9 9 7 11 9 10 16 9 9 11 16 10 11
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CBA or CAB
A or B 2 2
A or B
B or A 1 2 2 2 3
SBA or SAB (Note 5)
A or B
Enable GBA
A 2 2 3 3
Enable GAB
B 2 2
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6
DM74AS651 * DM74AS652
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M24B
7
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DM74AS651 * DM74AS652 Octal Bus Transceiver and Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com


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